The invention relates to an electronic circuit comprising: a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects, a main unit for implementing a normal mode function of the electronic circuit, and a test unit for testing the interconnects, the electronic circuit having a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit.
The invention further relates to a method of testing interconnects between a first electronic circuit and a second electronic circuit, the first electronic circuit comprising a main unit implementing a normal mode function of the first electronic circuit, and a test unit for testing the interconnects, the method comprising the steps of logically connecting the test unit to the interconnects, and putting test data on the interconnects by the second electronic circuit.
Such a circuit is known from xe2x80x9cBoundary-scan test, a practical approachxe2x80x9d, H. Bleeker, P. van den Eijnden and F. de Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5, FIGS. 1-19, which shows an integrated (IC) in accordance with the boundary-scan test standard IEEE Std. 1149.1. The known circuit has a main unit or core logic that is responsible for providing some arbitrary specified function in a normal mode of the circuit. The known circuit further has a test unit for in a test mode performing an interconnect test, i.e. a test whether the circuit is properly connected to a further circuit via its I/O nodes or IC pins. Efficient interconnect test of miniaturised and/or complex circuit assemblies is a necessary part of the production process of such assemblies. The boundary-scan test technique is accepted as standardised solution for interconnect test. It is available in most of the leading microprocessor families and is supported for in-house developed application specific ICs through automated tools in the IC design process.
The test unit of the known boundary-scan circuit includes a test control unit or Test Access Port controller and a shift register or boundary-scan register along the circuit boundary, cells of the shift register being connected to I/O nodes corresponding to the interconnects to be tested. The test control unit has a state machine controlling states of the shift register, examples of such states being a shift state for shifting in/out data into the shift register and a capture state for capturing data originating from the interconnects into the shift register. The shift register is accessible from outside the circuit via a Test Data In (TDI) node and a Test Data Out (TDO) node. A Test Clock signal (TCK) and a Test Mode Select signal (TMS) are provided from outside the circuit to the test control unit for stepping through the various states. In the normal mode of the known circuit, the I/O nodes are logically connected to the main unit, thereby allowing the circuit to perform its normal mode function. In the test mode of the known circuit, the I/O nodes are logically connected to the test unit, thereby giving the test unit access to the interconnects.
Provided that also the further circuit is equipped with a test unit in accordance with the boundary-scan test standard, the interconnects between the two circuits can be tested according to the standard boundary-scan test method. Hereto, appropriate test data is first shifted into the shift registers of the two circuits and is subsequently applied to the interconnects. Then, response data originating from the interconnects is captured into the shift registers and subsequently shifted out of the shift registers for observation. From the response data it can be determined whether the circuits are properly interconnected. For a single interconnect this means that to one of its ends a signal is applied and at the other end it is observed whether that signal is transmitted. In this way, an open circuit in an interconnect can be found. Additionally, a number of test patterns will be applied to the interconnects in order to check for short-circuits between neighbouring interconnects, or between an interconnect and a power supply line. Essentially, interconnect testing comes down to applying test data to one end of an interconnect and observing response data at another end, in such a way that open circuits and short circuits are detected.
A problem with the boundary-scan approach is that for some circuits pin count and pin compatibility considerations inhibit the addition of extra pins to a circuit design for the TCK, TMS, TDI, TDO and the optional TRSTN signals. Moreover, the price-pressure in some semiconductor fields is such that it is considered to be too expensive to reserve area for interconnect test of the size as required by boundary-scan circuitry.
It is an object of the invention to provide a circuit as specified in the preamble, that allows interconnect testing with reduced overhead in terms of required I/O nodes and/or area. This object is achieved according to the invention in an electronic circuit, which is characterised in that in the test mode the test unit is operable as a low complexity memory via the I/O nodes. Low complexity memories are those memories that do not have to be put through a complex initialisation process before they can be accessed, and that have simple access protocols without dynamic restrictions. Such a test unit enables an alternative procedure for applying test data to one end of an interconnect and observing response data at the other end. If the low complexity memory has a read-only character and holds pre-stored test data at a number of addresses, the test unit produces this pre-stored test data at its side of the interconnects when address data and appropriate control data are applied to it by the further circuit via the interconnects. The further circuit then receives response data, which should be identical to the pre-stored test data. In this way, both the interconnects that are used to carry the address and control data and the interconnects that are used to carry the pre-stored data itself are tested. It is important that particular input data for the test unit, i.e. the address, result in output data from the test unit that are known a priori, i.e. the stored data. If the low complexity memory allows both read and write access, the further circuit can apply test data to its side of the interconnects in a write mode of the test unit, thereby storing the test data in the test unit. In a subsequent read mode of the test unit, the further circuit can read back response data.
Whether the test unit has a read-only or a read/write behaviour, it does not need a state machine like the boundary-scan state machine and can therefore be implemented consuming less area. Moreover, the simple operation of the test unit allows less pins or even no pins at all to be reserved for controlling the test unit in the test mode. For both a read-only and a read/write test unit, a subset of the interconnects is used as a data bus for exchanging the storage data. At least in the case that the test unit has a read/write behaviour, a further subset of the interconnects is used as a control bus, including, for example, control lines for controlling the read and/or write process. At least in the case that the test unit has a read-only behaviour, a still further subset of the interconnects is used as an address bus for selecting the storage location to read from. An important aspect of the invention is that one is free how to map the data bus, the control bus and/or the address bus on the interconnects to be tested.
Access to the control bus, the address bus, and the data bus during test mode could be provided, for example, via boundary-scan circuitry of the further circuit. Then, with ordinary boundary-scan test equipment, data can be shifted in and out of the further circuit. In this way, data to be supplied to the control bus and/or the address bus and data returned by the test unit on the data bus can be handled. As a further example, if the further circuit is a programmed microprocessor or Application-Specific IC (ASIC), the further circuit could perform the interconnect test in a stand alone fashion, without the need for external equipment for feeding the further circuit with the test data and for evaluating the response data. It is noted that the further circuit alternatively could consist of two or more separate circuits, together operating the test unit as a low complexity memory.
An embodiment of the electronic circuit according to the invention is defined in claim 2. A Read-Only Memory (ROM) is a suitable device for holding the data required by the interconnect test. When control data, in the form of an address and, if necessary, a limited number of further control signals, is applied to the circuit, the ROM outputs data pre-stored at that address on the data bus. It will be clear that in this way both the data bus, the address bus and, if present, the control bus are tested. A small number of test patterns pre-stored in the ROM would normally suffice for an interconnect test capable of detecting open circuits in interconnects and short circuits between interconnects. It will further be clear that for the test unit being operable as a low complexity memory, it is not required that the test unit is implemented as a real ROM table. Especially if only a small number of test patterns is used, the test unit could be implemented as a combinatorial circuit, leading to more efficient area usage.
An embodiment of the electronic circuit according to the invention is defined in claim 3. In relation with such a read/write register, the control bus at least controls whether the register is in a read mode or in a write mode, and the data bus is used for both supplying the data to be written to the test unit and for receiving the data to be read back from the test unit. In this embodiment, no address bus is needed since only a single register is used.
An embodiment of the electronic circuit according to the invention is defined in claim 5. The test circuit of this embodiment requires comparatively little area of the substrate on which it is manufactured. Furthermore, it enables to test the interconnects in a single type of test and with a very good test coverage, i.e. a small set of patterns suffices to detect the possible defects in the interconnects. Furthermore, the diagnostic resolution of the test is very good since almost all faults have a unique signature.
High complexity memory devices are those devices which have complex protocols for reading from and writing into their memory array. Therefore, as opposed to low complexity memories, high complexity memories are not suited as test units for interconnect testing, as the process of exchanging data is too complex and therefore takes too much time. Examples of high complexity memory devices are Synchronous Dynamic Random Access memories (SDRAMs) and non-volatile memory like flash memory devices. Besides complex access protocols, high complexity memories often need initialisation and have dynamic restrictions. The initialisation is troublesome for testing because (almost) all control lines and address lines have to be connected correctly to succeed in initialisation. Although interconnect problems with control and address lines can be detected because the failing initialisation will block all access to the devices, the diagnosis of the failure, i.e. exactly which of the pins is not connected correctly has a very low resolution.
The dynamic restrictions of SDRAMs, usually identified by the refresh time and the maximum RAS pulse width, hamper interconnect test because the test patterns (i.e. writing into and reading from the memory array) have to meet the dynamic requirements. The speed of application of test patterns using a boundary-scan circuit is determined by the length of the boundary-scan register and the maximum test clock frequency. The test clock frequency is determined either by the circuit implementation of the boundary-scan circuit in the ICs on the board or by the maximum speed of the boundary-scan tester.
For these reasons, high complexity memories form a class of circuits that could very well benefit from adding a low complexity memory for enabling efficient interconnect testing. This is especially true because boundary-scan is hardly available in memory devices due to pin count and/or pin compatibility considerations.
An embodiment of the circuit according to the invention is described in claim 6. This particular way of activating the test mode is possible because in most SDRAMs the first action to be performed after power up is prescribed to be a write action. Thus at power up, by utilising the read action for activating the test mode, the normal operation of the SDRAM is not effected. As an alternative, the circuit in accordance with the invention can be brought into test mode via a particular combination of input signals on the I/O nodes, or via a dedicated node that is dedicated to this function.
Non-volatile memories like flash memory devices hamper interconnect test, because writing into the memory array for test purposes is not allowed when the device is already pre-programmed. This test would destroy the functional data. An un-programmed device can be written into but has to be erased afterwards. Erasure of large memory blocks can take up to several seconds, lengthening considerably the board interconnect test.
By including a test unit in accordance with the invention, high complexity memories, including non-volatile memories, can undergo an efficient interconnect test. One could use the normal mode data bus, address bus and/or control bus for the test mode as well. To also test interconnects that provide signals that are specific for the high complexity memory functionality, and therefore are not needed to control the test unit in the test mode, either the data bus or the address bus can be extended with these interconnects. The invention enables interconnect testing using test patterns which take only milliseconds to execute and for which test pattern generators are commercially available.
Low complexity memory types like Static Random Access Memories (SRAMs) and (Programmable) ROMs can readily be tested for their connectivity using neighbouring circuits equipped with boundary-scan or neighbouring microprocessors and/or ASICs. For interconnect testing of such low complexity memories no extra measures in the form of added test units have to be taken.
It is a further object of the invention to provide a method as specified in the preamble, which performs the interconnect test with reduced overhead in terms of required I/O nodes and/or area. This object is achieved according to the invention in a method, which is characterised in that the putting step comprises operating the first electronic circuit as a low complexity memory by the second electronic circuit.
Although the invention is presented in the context of boundary-scan testing, which mainly applies to testing interconnects between ICs on a carrier, such as a printed circuit board (PCB), the principles of the invention are equally applicable to the testing of interconnects between any two circuits, such as interconnects between cores within a single IC or interconnects between ICs on distinct PCBs that are inserted into a cabinet.